The present invention is particularly applicable to test equipment for testing semiconductor memories to make possible the continuous testing of memories at a wafer probe stage or as packaged parts for the purpose of their subsequent repair by means of a laser repair means.
The present invention is particularly applicable to test equipment for testing semiconductor memories to make it possible the continuous testing of memories at a wafer probe stage or as packaged parts for the purpose of their subsequent repair by means of a laser repair means.
In the semiconductor industry, devices are fabricated on silicon wafers, typically from 6 to 12 inches in diameter, with typically 400 die per wafer. These are tested using automated test equipment (ATE) driving the die and measuring the response. Each memory device under test is tested by means of a pattern generator generating a sequence of addresses for accessing and exercising the memory matrix. Failure data resulting from comparison of the actual data from the memory under test with expected data is then stored in a second memory for the purposes of repairing procedure or for engineering purposes.
Different schemes of performing testing may be used depending on a test pattern and the type of memory used for storing fault data. During the test process, the location of defective cells in the main memory may be identified to enable the subsequent repair of the device. Other applications of memory test include the examination of electrical and/or functional parameters of the memory for engineering or quality control purposes, or verification of the operation of the memory in different fields of end application.
A test system used for testing memory devices should be able to test each new generation of memory devices at the maximum speed of the new device. When the latest generation of memory devices is manufactured, there should be a test system available which is capable of testing these new memory devices. The test systems shall also be able to record a large number of locations. These factors combine to create a requirement for a large and expensive memory (called the fault capture memory or error catch RAM) in test systems because the fault capture memory must be the same size and operate at the same speed as the memory device under test.
To reduce the amount of RAM, some ATE manufacturers have used a FIFO memory for temporarily storing the fault information. For example, a known memory tester, the xe2x80x9cMinitester Bxe2x80x9d produced by Memory Corporation plc, uses a buffer memory for storing fault data, implemented in a FIFO memory, i. e. first-in-first-out memory. Other examples are Mosaid MS 4100 series tester also using a FIFO, and a tester built by EDA, Italy, which may stop when the FIFO is full. Still another example is a Honeywell INc. system (U.S. Pat. No. 4,718,004) using FIFO buffer for data acquisition. The more detailed description of such type of a memory may be found in xe2x80x9cTesting and Testable Design of High-Density Random Access Memoriesxe2x80x9d by Pinaky Mazumder and Kanad Chakraborty, Kluver Academic Publishers, Boston, 1996.
Known is a testing apparatus using a buffer memory for acquiring fault data (see EP-A-0149048), further comprising a means for avoiding the small buffer memory being overfilled by signaling the tester when the number of words read into the buffer exceeds some predetermined value. However, in the known system, the buffer cannot be read when the fault information is written and thus, cannot provide fast fault data transmission to the central control unit.
In another ATE using a buffer memory for storing fault addresses, fault information transmission may be started as soon as the first block of information is formed that saves time greatly. Another important feature of the use of a buffer is that the information about defective cells only is transmitted, not information on all cells, allowing usage of small RAMs as the buffer memory. However, in some cases, where memory under test has a lot of defects, the buffer memory can fail to operate adequately. For example, the above xe2x80x9cMinitester Bxe2x80x9d has a buffer memory of only 40 registers. This means that once a block of 40 defects occurs, the whole timing system halts or slows down, which can cause the rest of the device to look defective because the device is now operating outside the device""s timing specification.
Another well-known type of ATE (see e. g., U.S. Pat. No. 4,460,999) includes usage of a bitmap memory for storing fault information. In bitmap ATE schemes each memory cell has a corresponding row and column address in the bitmap memory. The block scheme and display chart of a typical ATE having bitmap memory for storing fault addresses is shown in FIG. 1. As seen in FIG. 1, a device under test (DUT) 1 is tested by an ATE system 2 with a fault memory capability in the form of a bitmap fault RAM 3. A timing system 5 generates addresses for accessing the DUT. An error capture system 4 is controlled by a central control unit C. The information obtained from the error capture system 4 is stored and/or displayed in the fault RAM 3. The bitmap fault RAM 3 contains the full information about a memory under test, therefore, no situation may occur with overfilling the buffer memory. Another example of a fault bitmap operating at a full tester speed is described in U.S. Pat. No. 5,790,559.
However, the use of a bitmap memory has significant disadvantages. First, bitmap fault memory is large and expensive, which increases the test time cost per memory device. This fault capture memory normally comprises Static RAndom Access Memory (SRAM) and can cost 30% of the total hardware cost of the test system. Second, the bitmap system requires long transferring time even when only a small part of the memory cell is defective. As seen from the picture, one more disadvantage is that fault information transmission can be started only after the whole test is completed, which results in a significant increase of the test time. It is therefore highly desirable to fine an alternative of using large fault capture memory.
The advantage of the present invention is the ability of an ATE system using a small buffer memory to avoid overflow and provide accessible continuous test of a memory device. The buffer memory may be implemented as, but not limited to, a FIFO memory, a single buffer, a double buffer, or multiple buffered circular buffers.
The substance of the present invention is a memory test system adapted to manipulate a timing means in case the buffer memory is full or nearly full. The timing means may be either suspended or slowed down until the buffer memory is at least partially freed. The free space size shall not be less than the maximal possible fault number corresponding to the smallest test pattern, i.e. the test pattern that cannot be interrupted in the course of test proceeding. The important feature of the present invention is that the timing means, being paused, is capable of maintaining properly refresh and clock functions for semiconductor devices. This feature is especially significant for DRAM""s, in which case timings, distributed refresh, the maximum interval between burst refresh and clocks are observed.
Thus, in one aspect, the invention is a memory test system comprising a central control unit, a timing means for generating a pattern of addresses, data and control signals for accessing memory elements, a fault logic means for detecting failures in the memory elements and a fault capture memory for storing the resulting fault information, including a high speed buffer memory and a low speed main memory, wherein the high speed buffer memory is operable so that as soon as the first portion of information about faults is received from the fault logic means, information transmission to the central control unit begins and the processing of the information in the main memory is started, while the timing means is signalled when the buffer memory is full or nearly full and stopped or slowed down except for a set of signals maintaining properly refresh intervals within the memory. In accordance with the preferred embodiment, the buffer memory is a FIFO type memory. Preferably, the test system is provided with a means for encoding the fault information to reduce a transmission time. Encoding means are typically a hardware means for assigning each fault vector an identification tag for subsequently storing and transferring this tag.
Another aspect of the present invention is a method of testing semiconductor devices, including a step of generating by a timing means a pattern of addresses, data and control signals for accessing memory elements within the device, a step of detecting failures in the memory elements and a step of processing the resulting fault information, including a step of a high speed processing in buffer memory and a step of a low speed storing and/or displaying in the main memory, wherein the processing of the information is performed so that as soon as the first portion of information about faults is received by the buffer memory, information transmission to a central control unit begins, and the processing of the information in the main memory is started, while the step of generating a pattern of addresses, data and control signals further includes a step according to which the timing means is signaled when the buffer memory is full or nearly full and stopped or slowed down except for a set of signals maintaining properly refresh intervals within the memory (1). In accordance with the preferred embodiment the buffer memory used is a FIFO type memory.
Still another aspect is a computer program for decoding fault information encoded by a hardware encoding means.